Advancements in the technology of integrated circuits have enabled designers to place relatively large numbers of digital logic gates as an array on a single integrated circuit chip (IC). Numerous approaches have evolved for interconnecting the logic gates of such high density, digital logic ICs.
A first approach, which may be described by terms such as hard-wired interconnection, metal interconnection, etc. and is referred to herein as mask-defined, uses the fixed layout of various conductive paths in the IC that are either diffused in the substrate or patterned in metallization layers of the IC to interconnect input and output terminals of logic gates, one to the next. As integrated circuit devices have become able to perform more functions within a single integrated circuit chip, the manufacturers of integrated circuit chips have developed ways of automatically and quickly responding to orders for custom chips to perform specific functions for specific applications.
Mask programmed gate array manufacturers apply custom metallization layers as a final step in a standard manufacturing process in order to connect transistors located within a semiconductor substrate to perform a particular logic function ordered by a customer. Manufacturers also provide fully custom integrated circuit devices in which the entire layout of the chip is selected to meet the needs of the customer. The terms "MPGA" and "ASIC" (application specific integrated circuit) are used in the industry to refer to integrated circuit devices for which the design is completed before manufacturing is completed and the IC is not programmable later. For the customer with a finalized design intended for long term, large volume production, custom metallization or full custom design can be an excellent choice. On the other hand, for customers who make frequent design changes, who want only small numbers of identical devices, or who may not yet have fully tested a new design and remain in the early stages of a product's life cycle, field programmable integrated circuit chips are available. In one form of a field programmable chip, there are many pass transistors which can be turned on or off to connect or not connect corresponding lines to logic circuits, to other lines, or to input/output pads. By turning on the proper combination of pass transistors and connecting the proper set of lines, a user can obtain a desired function. The user can reprogram a different design into the chip by turning on different combinations of pass transistors. In another form of programmable chip, interconnection of metal lines can be achieved through a field programmable via connection typically known as an antifuse.
The field programmable approach loses its advantage over the mask-defined approach in later phases of a product's life cycle when demand for the product grows, uncertainty about the design disappears, and chips need to be produced in relatively large volumes (i.e., 10,000 units or more). The total cost of the chip at such a point in its life cycle tends to be greater when the chip is a field programmable IC rather than a mask-defined chip. One reason field programmable chips have larger overall cost is that the memory cells and pass transistors in field programmable chips consume large amounts of space compared to the simple metal process used in mask-defined chips.
Xilinx, Inc., the assignee of the present invention, manufactures field programmable gate arrays or FPGAs. A Xilinx FPGA includes an array of logic blocks, each of which can be configured to perform a desired logic function (each logic block combining multiple AND, OR, MUX gates, or FLIP-FLOPs for example). The Xilinx FPGA also includes interconnect lines which can be programmed to interconnect individual logic blocks to achieve the overall complex logic function provided by the entire chip. In the current Xilinx products, two kinds of configurable blocks are used in an FPGA. Around the perimeter of the chip, and connected to each of the external pins are input/output logic blocks which can be programmed to connect input buffers or output buffers to the pin and to perform some logic functions. In the interior of the chip are logic blocks which offer user definable logic functions.
FIG. 1 shows the top left corner of an FPGA. Configurable input/output blocks IO2 through IO15 are shown. Configurable logic blocks CLB11-CLB14; CLB21-CLB24; CLB31-CLB34; and CLB41-CLB44 are shown. Each of the configurable blocks can be programmed to implement a plurality of logic gates such as AND, OR, XOR, INVERT, mixed combinational functions, and MUX as well as tristate buffers and FLIP-FLOPs and can be combined to implement a plurality of more complex logic functions.
One type of logic block includes a look-up table which is programmed to provide a desired function of several input signals. By loading memory cells of a look-up table with the truth table of a desired logic function, any logic function of its input signals is obtained. This block gives great flexibility with minimal signal delay.
These configurable blocks each have input and output leads for receiving input signals and providing output signals. These leads are shown in FIG. 1 as short lines extending outward from each of the blocks and not connected to other portions of the array. An interconnect structure not shown in FIG. 1 is also present, and can be programmed to connect these short lines to each other. The configurable logic array chip also has a configuration structure not shown in FIG. 1 for programming the particular logic function or loading a truth table. Loading memory cells in the configuration structure determines what logic function will be applied by the block to signals on its input leads to generate a signal on its output lead or leads. These logic blocks are discussed in U.S. Pat. No. 4,706,216 issued Nov. 10, 1987, which is incorporated herein by reference.
While FPGA designs such as the one illustrated in FIG. 1 are highly configurable, there remains a need in the industry for less expensive programmable chips with higher equivalent logic gate density per area of silicon. While purely programmable devices are becoming less expensive than they were, if large numbers of devices are needed and the design is fixed and well-known, mask-defined chips are still less expensive than field programmable devices of equivalent gate count. To accommodate a nearly completed design and the remaining evolution of the design to final stage wide spread distribution, there is, accordingly, a need in the industry for a device which allows for inexpensive large scale production of customized chips while permitting the user a limited form of post-fabrication modification of the design.